The present invention lies in the fields of semiconductor devices and methods for fabricating semiconductor devices, especially in the field of MOS and bipolar devices produced according to these methods. More particularly, the present invention lies in the field of methods for fabricating fully planarized MOSFET structures.
Modern integrated circuit fabrication is a multistep process involving deposition and/or growth of multiple layers, each of which is patterned by photolithography and etching to form the three-dimensional elements that comprise a semiconductor device. For modern devices, the photolithography process must be capable of delineating features of 0.5 .mu.m or less. Such resolving power requires a total depth of focus of slightly more than 1 .mu.m. Ideally, each layer should be sufficiently planar that no regions of the surface will fall outside of this focus range. Unfortunately, current methods of fabricating metal oxide semiconductor field effect transistors ("MOSFETs"), do not typically produce highly planar layers. As a result, the minimum possible feature widths are not realized, and the packing density and current output of the device suffer.
In most fabrication processes, a field oxide is initially grown by LOCOS (local oxidation of silicon) or a related procedure to electrically isolate the "active areas" where devices are formed on the substrate surface. The resulting structure consists of an island of silicon (the active area), surrounded by a thick (approximately 0.5 .mu.m) region of field oxide, elevated above the plane of the substrate. Thus, a "stepped" surface is produced in the very first fabrication step. If this surface is not somehow planarized, each subsequent layer will also contain steps.
By pre-etching the substrate surface, field oxides can be grown that are substantially coplanar with the substrate surface. These processes are, unfortunately, more expensive than traditional LOCOS and are, therefore, not favored. Alternatively, LOCOS can used in conjunction with a planarization step that removes the top of the field oxide layer and produces a planar surface. However, planarizing the relatively hard field oxide layer to exactly the correct depth (i.e., the original level of the substrate) is expensive and time-consuming, especially if an abrasive process such as chemical-mechanical polishing is employed. Thus, most fabrication processes continue to use substrates having the stepped surfaces produced by LOCOS.
After the field oxide has been grown, circuit elements are formed within the active region pockets by a variety of well-known techniques. For example, early in the fabrication process, the substrate may be doped by ion-implantation or diffusion to form local regions of increased conductivity. Such procedures are described in, for example, in U.S. Pat. No. 4,764,480 (issued to Vora and assigned to the assignee of this invention) which is incorporated herein by reference for all purposes. Another early fabrication step is local formation of a thin gate oxide layer on the active silicon areas. Because this material is thin in comparison to the field oxide it does not significantly contribute to the overall planarity of the layer.
After the gate oxide has been formed, a layer of polycrystalline silicon ("polysilicon") is typically deposited over the entire substrate surface. This process is described in, for example, U.S. patent application Ser. No. 502,943 which is assigned to the Assignee of the present invention and incorporated by reference herein for all purposes. The polysilicon surface is then patterned by photolithography and subsequent etching to form MOSFET elements and interconnects. Unfortunately, the stepped topography of the underlying substrate and field oxide is transferred, in part, to the surface of the polysilicon layer during deposition, and shows up as height variations on the new surface. These height variations are, in turn, translated into height and thickness variations in the photoresist layer. The resist height variations cause focus variations in the projected optical image, while the resist thickness variations cause differences in the optimum amount of optical energy required to expose the full depth of the resist. Thus, strips of photoresist which cross from field areas to active areas over the steps are difficult to expose properly.
An entirely different problem is also caused by depositing polysilicon on nonplanar surfaces. The conformally deposited polysilicon layer is actually thicker over the step regions than over other regions. Thus, in subsequent etch steps, the polysilicon over the thin gate oxide is cleared before the polysilicon over the steps. Although etch conditions are tailored to remove polysilicon faster than oxide, the gate oxide and underlying substrate can still be damaged while the extra polysilicon is being removed from the steps. As a result, the process yield and MOSFET reliability may be reduced.
During etch steps, polysilicon is cleared from the source and drain areas, leaving a narrow central strip of material called the gate. This process thus divides the active region into three parts: the gate area, the source area, and the drain area. In most conventional processes, the exposed regions of the active area are then doped to form source and drain regions of the MOSFET. Next, a layer of dielectric material is deposited over the entire wafer. The surface of this layer is, of course, non-planar like the surface below it. Subsequent photolithography steps used to define openings in the dielectric layer (for metal contacts to the source and drain regions and to the gate metal strips) must therefore contend with the undulations of the dielectric surface. In addition, the dielectric layer is now substantially thicker over the source/drain areas than over the polysilicon on the field oxide. Contact holes must eventually be etched through the dielectric layer to reach both of these areas. Unfortunately, the thickness variations in the dielectric layer complicate this step.
As can be seen from the above discussion, each new process step tends to exacerbate the problems of the previous step. As additional layers are added during the fabrication process, the uneven surface at the bottom of the device propagates, at least in part, to the higher levels of the device. In some instances, the surface roughness actually becomes worse with each succeeding layer. The etch processes further complicate the procedure by introducing new protrusions and valleys that propagate upward during fabrication.
Several methods exist to alleviate one or more of these undesirable features. First, as explained above, some methods produce a field oxide that is coplanar with the active areas, thus reducing the severity of the surface height variations. Examples of such methods include the "ISOPLANAR" technology coupled with a planarization step, as discussed in U.S. Pat. No. 4,764,480, (previously incorporated herein by reference), the "SWAMI" technology described by Chiu, et al., IEDM, 1982, p. 224, and a planarized shallow trench isolation technology described by Davari et al., IEDM, 1988, p. 92. All of these are more elaborate and costly than the simple and widely-used LOCOS process. Alternatively, LOCOS can be used in conjunction with planarization of a subsequently deposited polysilicon layer. This approach is described in U.S. patent applications Ser. No. 07/880,880 and Ser. No. 07/874,493, which were previously incorporated herein by reference. Other approaches involve planarizing the dielectric layer deposited over the etched polysilicon layer. This can be done by "reflow" (a process in which the wafer is heated to a high enough temperature to cause the dielectric to redistribute itself on the surface), or by spin coating with a sacrificial layer and etching back. However, these approaches produce imperfect planarization. Alternatively, chemical-mechanical polishing (CMP) can be used to planarize the dielectric layers. Unfortunately, CMP planarization of dielectrics is relatively expensive, and it does not address the problem of different contact hole depths.
A radically different method for producing a completely planar structure was proposed by Wen et al. in Proc. 1991 VLSI Symposium, p. 83. In their method, oxide-filled deep trenches are produced by a planarized trench isolation technology such as described by Davari, et al. Technical Digest of 1989 IEDM, p. 61. Presumably, the top surface of these oxide trenches will be coplanar with the surrounding silicon substrate. Next, an unconventional reactive ion etching (RIE) process is used to etch grooves where polysilicon runners are desired. These grooves must traverse both the active silicon areas and the trench fill oxide areas. Thus, the etch process must remove silicon and silicon dioxide at exactly the same rates to ensure that a flat groove bottom is produced where the runner crosses from field to active regions. On the silicon regions of the grooves, a thin gate oxide is grown. A layer of polysilicon is thereafter deposited over the entire surface, and CMP is used to polish it back to the top of the groove. Thus, according to Wen et al., a planar MOSFET is produced.
Although Wen, et al. have described a fully planar process, it suffers from certain difficulties. First, the technique for preparing oxide-filled deep trenches is expensive and difficult to perform. Second, the etch process must remove oxide and silicon at identical rates. Such processes have proven quite difficult to control. Third, the thin gate oxide must be grown in the bottom of an etched groove in the silicon, a difficult process which does not assure a high integrity oxide. Fourth, the areas where the source and drain regions of the MOSFET meet the channel region over the gate are buried by the deposited layer of polysilicon. Thus, the doping profiles of the source and drain can not be aligned with the gate during ion implantation, and the method must rely on diffusion alone to tailor the profiles.
Thus, it is seen that improvements are still needed in the MOSFET fabrication procedures.